1. Field of the Invention
This invention relates to the field of integrated circuit testing. More particularly, this invention relates to scan chain cells which are used to apply stimulus signals to, and capture result signals from, signal nodes within integrated circuits.
2. Background of the Invention
It is known to provide scan chain cells arranged in serially connected scan chains through which stimulus signal values or result signal values may be serially clocked. This is a convenient way to test complex integrated circuits. As the complexity of integrated circuits increases, they are often formed of a collection of different functional units with some of those functional units being disposed within the integrated circuit such that it is not possible to directly apply signals as inputs to those functional units through an external connection to the device. In these circumstances, scan chain cells are particularly useful for accessing the points (nodes) within an integrated circuit at which it is desired to apply a stimulus signal and from which it is desired to capture a result signal when those points are not otherwise externally accessible.
There is an ongoing progression within integrated circuit design to use increasingly small process sizes. These small process sizes enable higher densities of circuit gates to be achieved, reduce power consumption and increase performance. A drawback with the use of such smaller processes, e.g. 45 nm process sizes and below, is that the variability between individual gates becomes a more significant factor resulting in a lower yield of properly operating integrated circuits. In this context, test, such as manufacturing test, is becoming increasingly significant. One important aspect of integrated circuit performance that needs to be tested is the “at speed” performance to determine that processing logic within the integrated circuit is capable of operating at its design speed or to detect other types of defect that manifest themselves as an excessive delay. One way of viewing this test is that it is necessary to determine that the functional logic is capable of responding to changes in values of input signals sufficiently rapidly to generate the appropriate output signals without too large a delay which would cause an error in operation. This type of testing can be termed “delay testing”.
A problem exists in using conventional scan chain cells to apply stimulus signals for such delay testing. Scan chain cells are typically provided in a serially connected fashion and use a scan clock to shift signal values through the scan chain at a comparatively slow speed. Accordingly, changing a signal value at a stimulus node within an integrated circuit from one signal value to another signal value so as to cause a transition and test the delay time through a functional circuit is difficult to achieve by serially advancing differing signal values through the scan chain cell since the scan clock is typically not fast enough, and the gates within the scan cell chain are often made small and weak for area saving and power saving reasons. Even if the scan system is fast enough to shift at speed, there are other reasons why this may be undesirable, e.g. a requirement for a separate scan enable. It may also be undesirable to have to add multiple state holding elements within a wrapper cell to support rapid transition generation.